This invention relates to data processing apparatus and, more specifically, is concerned with a data processing apparatus including a cache memory.
It is well known to provide a two-level memory system, consisting of a main memory and a smaller, faster cache memory. In operation, the cache is arranged to hold copies of data items from the main memory that are currently in use, or are likely to be required in the near future, so that these items can be accessed rapidly, without the delay of a main memory access. Such memories are described, for example, "Cache Memories" by A. J. Smith, ACM (Association for Computing Machinery) Computing Surveys, Vol. 14, No. 3, September 1982, pages 473-529.
As described on page 479 of the above Computing Surveys article, in a computer system with virtual memory, the cache may potentially be accessed either with a real (or physical) address, or a virtual address. The advantage of using the virtual address is that it is not necessary to wait for the address to be translated before accessing the cache, and hence the cache access is faster. The address has to be translated only if the required data item is not present in the cache.
The translation of the virtual address may conventionally be performed by a memory management unit (MMU) comprising an associatively addressed memory holding address translation information (e.g. page table entries) for recently used virtual addresses. If the required address translation information is not present in the MMU, then the main memory is accessed, to read the required page table entry. Possibly several main memory accesses are required to translate an address.
A problem with this is that, since main memory access is relatively slow, the address translation process can take a relatively long time. The object of the present invention is to overcome this problem.